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進入《TAIPEI TIMES》 Powertech to build advanced packaging fab
Powertech Technology Inc chairman D.K. Tsai, fourth left, and guests yesterday attend a groundbreaking ceremony for its third plant at the Hsinchu Science Park. Photo: CNA
DECADE OF DEMAND: The fab would be the first in the world to commercially use FOPLP technology, which integrates different ICs more efficiently and economically
By Lisa Wang / Staff reporter, in Hsinchu
Memorychip tester and packager Powertech Technology Inc （力成科技） yesterday said it plans to invest NT$50 billion （US$1.63 billion） in the next five years to build an advanced fab for next-generation packaging technology, catering to growing demand for smaller and energy-saving chips for artificial intelligence, Internet of Things and autonomous vehicle applications.
Fab 3 in Hsinchu Science Park is to be the world’s first fab that commercially uses fan-out panel-level packaging （FOPLP） technology when it starts operations in the second half of 2020, Powertech said.
The announcement comes after Powertech’s major breakthroughs in commercializing the technology since it began secretly investing in it two years ago.
“It is becoming increasingly difficult and expensive to shrink transistor [geometry] even smaller ... to keep Moore’s law going,” Powertech chairman D.K. Tsai （蔡篤恭） told a media briefing, referring to an observation that processing power doubles every two years, while costs reduce by half.
“We believe FOPLP technology will be one of the solutions as the technology helps integrate heterogeneous ICs [integrated circuits] in a [smaller] system in an economical way,” Tsai added.
FOPLP technology is more cost-effective, compared with rival fan-out wafer-level packaging, as rectangular panels can be cut into more chips than 12-inch round wafers, Tsai said.
Taiwan Semiconductor Manufacturing Co （TSMC, 台積電） uses fan-out wafer-level packaging.
Asked whether Powertech would directly compete with the world’s biggest contract chipmaker, Powertech chief technology officer David Fang （方力志） said that the company’s targeted customers “might be different from TSMC’s.”
ASE Technology Holding Co （日月光投資控股）, the world’s biggest chip tester and packager, has said it is also developing FOPLP technology, but has not provided details.
Fab 3 is to create 3,000 jobs, the company said, adding that it is to have an installed capacity of 50,000 sheets a month, or 150,000 12-inch wafers.
“We have to invest in advanced technologies to support our growth and to survive,” Tsai said.
Fab 3 would satisfy burgeoning demand for new chip packaging technologies in the next decade, Powertech said.
The company plans to use its cash flow to finance construction of the fab, as it had NT$19.88 billion of cash on hand as of June 30.
Providing the company’s business outlook for next quarter, Powertech president Hung Chia-yu said that the fourth quarter would differ from previous years.
“The fourth quarter is usually the strongest season for Powertech, but this year, it will be very similar to the third quarter [in revenue],” Hung said.
Hung attributed the stagnation to customers’ inventory corrections.
Powertech in July and last month saw revenue jump 14.6 percent to NT$12.31 billion, compared with NT$10.75 billion in the same period last year, Taiwan Stock Exchange filings showed.
新聞來源：TAIPEI TIMES
